Test Generation Based on Testing

We propose a new test generation method in which the test vectors or test sequences are generated based on the predetermined testing prooles. A testing pro-le describes the Boolean function and the minimum test requirement of a cell which may be a gate in a gate level netlist or a VLSI cell from the standard cell library. The proposed testing method provides exi-bility in dealing with diierent fault models, such as stuck-at, stuck-open, bridging, etc., by simply changing the contents of testing prooles. 1